Title :
VENUS - A Fully Automatic Design System for Complex Cell and Gate Array Chips
Author :
Vollmer, H. ; Blondin, K. ; Koch, B. ; Hernandez, M. ; Müller, R.
Author_Institution :
Siemens AG, Munich, Corporate Laboratories for Information Technology
Abstract :
A semicustom VLSI design system is presented. Hierarchical chip designs of complexities up to 50.000 equivalent gates are supported when using parameterised general cells like RAM, ROM or PLA. The CAD tools of VENUS include automatic scan path routing, automatic placement and routing of general cells and test pattern generation.
Keywords :
Chip scale packaging; Circuit simulation; Delay; Libraries; Programmable logic arrays; Read only memory; Registers; Routing; Timing; Venus;
Conference_Titel :
Solid-State Circuits Conference, 1985. ESSCIRC '85. 11th European
Conference_Location :
Toulouse, France
