• DocumentCode
    516466
  • Title

    9K 150 ps-Gates on an ECL Masterslice Cell Array

  • Author

    Gonauser, E.

  • Author_Institution
    Siemens AGMunich, FRG
  • fYear
    1985
  • fDate
    16-18 Sept. 1985
  • Firstpage
    401
  • Lastpage
    405
  • Abstract
    A bipolar masterslice cell array with 9K gate complexity has been developed. The 128 mm2 chip features ECL100K/10K compatibility, 20 W typical power dissipation, and 320 pins (256 logic, 64 supply). The on-chip gate delay is 150 ps.
  • Keywords
    Crosstalk; Delay effects; Integrated circuit interconnections; Logic; Macrocell networks; Metallization; Pins; Power dissipation; Resistors; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1985. ESSCIRC '85. 11th European
  • Conference_Location
    Toulouse, France
  • Type

    conf

  • Filename
    5468185
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516466