• DocumentCode
    516475
  • Title

    The Static Noise Margin of SRAM cells

  • Author

    List, F.J.

  • Author_Institution
    Philips Research Laboratories Eindhoven, Nederlandse Philips Bedrijven B.V., P.O. Box 80.000, 5600 JA Eindhoven, The Netherlands.
  • fYear
    1986
  • fDate
    16-18 Sept. 1986
  • Firstpage
    16
  • Lastpage
    18
  • Abstract
    A simulation method is presented which makes it possible to analyze the stability of SRAM cells in terms of Static Noise Margin (SNM). With this method the effect of supply voltage reduction below the conventional 5V on the stability of resistor load (R-load) and full CMOS (6T) SRAM cells is analyzed. Simulations are carried out with estimated transistor parameters of a sub-micron process. From the results it is concluded that full CMOS cells are much more stable at low supply voltages.
  • Keywords
    Analytical models; CMOS process; Flip-flops; Inverters; Noise figure; Noise reduction; Random access memory; Resistors; Stability analysis; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1986. ESSCIRC '86. Twelfth European
  • Conference_Location
    Delft, The Netherlands
  • Type

    conf

  • Filename
    5468249
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516475