• DocumentCode
    516491
  • Title

    A 13ns/350mW 2Kw Ã\x97 9b RAM using Hi-BiCMOS Technology

  • Author

    Miwa, Hideo ; Yamauchi, Koudo ; Odaka, Masanori ; Ogiue, Katsumi ; Ide, Akira ; Yamamura, Masahiro

  • Author_Institution
    Hitachi VLSI Engineering Corp., Hitachi Ltd., Tokyo, Japan
  • fYear
    1986
  • fDate
    16-18 Sept. 1986
  • Firstpage
    41
  • Lastpage
    43
  • Abstract
    A 2-Kword × 9-bit, TTL-compatible, high-speed RAM has been developed using 2 ¿m Hi-BiCMOS technology. The RAM has an address access time of 13 ns, an active power of 350 mW, and a standby power of 40 mW. These characteristics have been achieved by overall use of Bipolar-CMOS combination circuits.
  • Keywords
    Bipolar transistors; CMOS technology; Capacitance; Decoding; Delay effects; Driver circuits; High power amplifiers; Power dissipation; Read-write memory; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1986. ESSCIRC '86. Twelfth European
  • Conference_Location
    Delft, The Netherlands
  • Type

    conf

  • Filename
    5468273
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516491