A Monolithic 1 to 50 MHz CMOS Clock Recovery and Retiming

This paper describes a novel single-chip design of a clock recovery and data retiming circuit. The chip, when used on the receiving end of a serial data link, recovers a clock from NRZ random data transmitted at any bit rate between 1 and 50 mb/s and synchronizes the clock with the data stream. The chip has been fabricated using a 1.75 micron twin-tub CMOS process and is packaged in a 20 pin plastic DIP which dissipates 250 mW with a single 5.0V supply. In serial data link applications, the chip can be exploited as an inexpensive and easy-to-use standard component to replace many HIC and PCB designs of clock recovery circuits that generally require several discrete components, expensive resonant elements, manual adjustments, and occupy large board space.