A Low-Voltage Multi-Bit DRAM Cell with a Built-in Gain Stage

A new high-density memory cell concept for storing analog information as well as digital data is proposed and experimentally demonstrated. This cell, composed of two transistors and one capacitor generates a large bit-line signal voltage at a supply voltage as low as 1.0V. Since this cell does not need a large storage capacitance and the pass-transistor can be stacked on the top of the amplifying transistor, the cell size can be easily scaled down for future generations of memory devices. To test the feasibility of this cell, we fabricated a test array using a 4M SRAM process without any process modification. The cell size was 1.8¿m×2.85¿m. A signal retention time of more than 400ms at room temperature is obtained from a cell with a capacitance of 2.5fF.