• DocumentCode
    516638
  • Title

    A 750 ks/s 8-Bit Low-Power Pipelined A/D Converter

  • Author

    Valencic, V. ; Deval, P.

  • Author_Institution
    Laboratoire d´´Electronique Générale, EPF, Lausanne, Switzerland
  • fYear
    1988
  • fDate
    21-23 Sept. 1988
  • Firstpage
    42
  • Lastpage
    45
  • Abstract
    A switched-capacitor pipelined A/D convertor is described, in which the amplifier offset compensation is inherent to the circuit structure and the effect of clock-feedthrough is as low as 0.5 mV. Preliminary experimental results, obtained on circuits fabricated using a low-voltage CMOS technology, indicate 8- bit resolution for 750 kHz sampling frequency, with only 5 mW power consumption.
  • Keywords
    CMOS technology; Capacitors; Circuits; Clocks; Energy consumption; Pipelines; Sampling methods; Switches; Switching converters; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1988. ESSCIRC '88. Fourteenth European
  • Conference_Location
    Manchester, UK
  • Type

    conf

  • Filename
    5468461
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516638