A 100 ns 4Mbit (512KÃ\x978bit) CMOS EPROM

This paper describes a high speed 4M bit CMOS EPROM with 100 ns access time, 512K × 8 bit organization, and 40 ¿s/word programing time. Polycide word lines, optimization of sense amplifier gain and anti-noise output buffer design are essential to shorten the access time. The chip is fabricated in 1.0 ¿m Nwell CMOS technology with double poly, single silicide, and single metal. To obtain pattern shrinkage, plugged contact structure is used. The chip size of 5.48 mm × 14.79 mm is accomplished.