DocumentCode
516648
Title
A 100 ns 4Mbit (512KÃ\x978bit) CMOS EPROM
Author
Kamaya, M. ; Higuchi, M. ; Urai, T. ; Ninomiya, K. ; Watanabe, T. ; Koyama, S. ; Jinbo, T.
Author_Institution
LSI Memory Division, NEC Corporation, Kawasaki, Japan
fYear
1988
fDate
21-23 Sept. 1988
Firstpage
23
Lastpage
25
Abstract
This paper describes a high speed 4M bit CMOS EPROM with 100 ns access time, 512K × 8 bit organization, and 40 ¿s/word programing time. Polycide word lines, optimization of sense amplifier gain and anti-noise output buffer design are essential to shorten the access time. The chip is fabricated in 1.0 ¿m Nwell CMOS technology with double poly, single silicide, and single metal. To obtain pattern shrinkage, plugged contact structure is used. The chip size of 5.48 mm × 14.79 mm is accomplished.
Keywords
Breakdown voltage; CMOS technology; Circuit noise; Design optimization; EPROM; Feedback circuits; Integrated circuit interconnections; Large scale integration; Lithography; Space technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1988. ESSCIRC '88. Fourteenth European
Conference_Location
Manchester, UK
Type
conf
Filename
5468475
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