Title :
Auriga2, a 4,7 Million Transistor CISC Processor for a High-End Mainframe
Author :
Tual, J.P. ; Thill, M. ; Bernard, C. ; Nguyen, H.N. ; Vallet, P.
Author_Institution :
Hardware Development Paris & Angers, BULL S.A., 78340 Les Clayes-sous-Bois, FRANCE
Abstract :
With the introduction of the high range version of the DPS7000 mainframe family. Bull is providing a processor which integrates the DPS7000 CPU and first level of cache on one VLSI chip containing 4.7M transistors and using a 0.5 m. 3M layers CMOS technology. This enhanced CPU has been designed to provide a high integration, high performance and low cost system. An architectural overview of the CPU with emphasis on several of its original features together with some physical design aspects are discussed in this paper.
Keywords :
CMOS process; CMOS technology; Costs; Data security; Energy consumption; Frequency; Hardware; Pipelines; Power system security; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference, 1994. ESSCIRC '94. Twentieth European
Conference_Location :
Ulm, Germany
Print_ISBN :
2-86332-160-9
