Area Efficient Viterbi-Decoder Macros

Viterbi decoders are widely used today for the decoding of convolutional codes used for reliable data transmission via satellite channels and proposed for bandwidth-efficient digital television scheme. If good error correcting capabilities are required (constraint length ≫ 6) todays state-of-the-art CMOS technology allows for the integration of complete digital receivers (in the 10 MBit/s data-rate range) on one chip except for the Viterbi decoder. The high speed Viterbi decoders nowadays are separate chips. Due to non-optimal matching of those Viterbi decoders to the throughput demands of the application they require a large area of ≫ 60mm² in 0.8¿m CMOS. In this paper we present the implementation results of area-efficient scalable Viterbi-decoder macros for one-chip digital receivers. We generate layouts for four industry-typical examples to determine exact area figures including wiring.