DocumentCode
516675
Title
20 Gb/s Monolithic Integrated Clock Recovery and Data Decision
Author
Wang, Z.-G. ; Berroth, M. ; Hurm, V. ; Lang, M. ; Hofmann, P. ; Hülsmann, A. ; Köhler, K. ; Raynor, B. ; Schneider, Jo.
Author_Institution
Fraunhofer-Institute for Applied Solid-State Physics, Tullastr. 72, D-79108 Freiburg, Germany. Tel: +49 761 5159 533, Fax: +49 761 5159 400
fYear
1994
fDate
20-22 Sept. 1994
Firstpage
176
Lastpage
179
Abstract
An IC for 20 Gb/s clock recovery and data decision was realised using 0.3 ¿m gate-length QW-HEMTs. A narrow-band regenerative frequency divider with on-chip resonator filters is used for the clock recovery. The parallel processing concept is accepted for the data decision. The complex IC was tested on wafer using 5 and 10-Gb/s input data. The desired 10-GHz clock signal and regenerated data signals have been obtained. The 2×2 mm2 IC has a power consumption of about 0.5 W at ¿3 volt supply voltage.
Keywords
Chromium; Clocks; Energy consumption; Frequency conversion; Narrowband; Passive filters; Phase locked loops; Resonator filters; Signal processing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1994. ESSCIRC '94. Twentieth European
Conference_Location
Ulm, Germany
Print_ISBN
2-86332-160-9
Type
conf
Filename
5468506
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