DocumentCode
516710
Title
Full RISC Approach for Test Ability
Author
Stefan, Denisa
Author_Institution
"Politehnica" University of Bucharest, Electronics & Telecommunications Dept., Bd. Armata Poporului 1-3, sector 6, Bucharest, Romania. e-mail: stefan@hera.gef.pub.ro
fYear
1995
fDate
19-21 Sept. 1995
Firstpage
418
Lastpage
421
Abstract
With increasing VLSI complexity, an alternative strategy, that has evolved, is to design in testability at the design stage. This paper deals with the RISC processor design for testability. The instruction set is defined, the processor logic design is performed and the on chip structure for test vectors generation, using the minimum area, is presented. We used the results of the algorithmic information theory to balance the complexity of machine with one of the test sequence, so that the area is minimised.
Keywords
Design for testability; Electronic equipment testing; Information theory; Logic design; Logic testing; Pipelines; Read only memory; Reduced instruction set computing; Registers; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1995. ESSCIRC '95. Twenty-first European
Conference_Location
Lille, France
Print_ISBN
2-86332-180-3
Type
conf
Filename
5468558
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