Title :
1 Gb/s clock recovery PLL in 0.5 μm CMOS
Author :
Rau, M. ; Oberst, T. ; Lares, R. ; Schweer, R. ; Menoux, N. ; Rothermel, A.
Author_Institution :
University of Ulm, Germany; Siemens AG, Munich, Germany
Abstract :
A clock recovery PLL is described for serial NRZ data transmission. The VCO works at only half the data rate, which means for a 1 Gb/s data rate the VCO runs at 500 MHz. A specially designed phase comparator uses both the rising and falling clock edges to compare clock and data. The VCO can typically be tuned from 350 MHz to 890 Mhz and the PLL locks between 850 Mb/s and 1.3 Gb/s. The circuit consumes 140 mW (3.3 V) at 1 Gbit/s including pad drivers.
Keywords :
Circuits; Clocks; Costs; Data communication; Digital signal processing; Energy consumption; Frequency; Optical signal processing; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 1996. ESSCIRC '96. Proceedings of the 22nd European
Conference_Location :
Neuchatel, Switzerland
Print_ISBN :
2-86332-197-8