Low-Power Logic Styles : CMOS vs CPL

Recently reported logic style comparisons based on full-adder circuits showed complementary pass-transistor logic (CPL) to be much more power efficient than conventional CMOS. New comparisons performed on more efficient CMOS circuit implementations and a wider range of different logic cells and by using realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, power dissipation, and power-delay (PT) products.