Title :
Push-pull Pass-transistor Logic Family for Low voltage and Low power
Author :
Paik, Woo-Hyun ; Ki, Hoon-Jae ; Kim, Soo-Won
Author_Institution :
ASIC Lab. Department of Electronics Engineering, Korea University, 5-1 Anam-dong Sungbuk-gu, Seoul, Korea, #136-701. Tel: 82-2-928-1216, Fax: 82-2-928-0179, E-mail: paikwh@asic02.korea.ac.kr
Abstract :
This paper describes a new pass-transistor logic family, named PPL(Push-pull Pass transistor Logic), for low voltage and low power which restores outputs by the push-pull operation. Using PPL circuits, 40-stage full adder chain and 8-bit multiplier are designed and fabricated in a 0.8¿m CMOS process technology. PPL achieves 36.4ns delay with the power consumption of 0.45mW/100MHz in the full adder chain and 112MHz speed with 30.4mW/100MHz power dissipation in the multiplier.
Keywords :
Adders; CMOS logic circuits; CMOS process; CMOS technology; Degradation; Delay; Energy consumption; Logic design; Low voltage; Signal restoration;
Conference_Titel :
Solid-State Circuits Conference, 1996. ESSCIRC '96. Proceedings of the 22nd European
Conference_Location :
Neuchatel, Switzerland
Print_ISBN :
2-86332-197-8
