Design Methodology for High Speed and Low Power Digital Circuits with Energy Economized Pass-transistor Logic (EEPL)

A new design method for digital circuits with Energy Economized Pass-transistor Logic (EEPL) is proposed. Adopting the principle of regenerative positive feedback with pMOS switches, we reduce the power and delay product (energy) in companson with CPL and SRPL. To demonstrate the performance of EEPL, a combinational circuit of a 54 × 54 bit multiplier whose multiplication time is 9.8ns and a sequential circuit of a 7-bit serial counter whose operating speed is 250MHz are designed with 0.6¿m 3.3V CMOS process.