Thermally Constrained Placement of Analog and Smart Power Integrated Circuits

This paper presents an algorithm for the performance driven placement of temperature sensitive analog integrated circuits. A simulated annealing algorithm is used to optimize ah initialy random placement. During each iteration of the optimization algorithm, the temperature distribution caused by power dissipating devices is calculated using an analytical multi-layer thermal model. The influence of local temperature differences on the performance of the circuit is then computed using sensitivity information and specification violations are penalized in the placer´s cost function. In this way, it is guaranteed that the thermally-induced performance degradation, such as offset, stays within the specifications of the designer. An industrial circuit is used to verify the algorithm.