VHDL timing model for CMOS semicustom branch-based logic cells

This paper presents a model for characterizing delay in semicustom CMOS logic cells that accounts for input slew rate and output capacitance loading. The logic cells are decomposed into branches of series connected transistors. A method for deriving the model parameters and VHDL modeling of the branches is presented. This method drastically reduces the number of model parameters required for delay characterization.