VLSI implementation of a bi-processor architecture for generic subband coding

This paper presents an architecture for the multiresolution coding of pictures. A VLSI implementation has been realized and can achieve a peak performance of about 500 MOPS. The architecture consists in 2 processors whose complementarity enables to avoid any wait cycles during the execution so that the available computation power is continuously used. Moreover, the circuit has a total programmability with respect to the used filters and the picture format; it also has the possibility to take edge effects into account and therefore improve the coding performances. The circuit can be used in the coding as well as in the decoding.