A Monolithic 19-Bit 800 Hz Low Power Multi-Bit Sigma Delta CMOS ADC using Data Weighted Averaging

This paper describes a sigma delta switched capacitor CMOS ADC using multi-bit quantization and feedback path for minimum power consumption. Multi-bit quantization has up to now been avoided because the linearity of the DAC in the feedback path directly limits the linearity of the whole converter. By using data weighted averaging, the non-linearity error related to the mismatch of the DAC components is decorrelated from the signal and transformed into high frequency noise. Hence most of this error is further eliminated together with the quantization noise by the digital lowpass filter.