Estimation of Ground Bounce in CMOS Circuits using a Solution to a Damped RLC Network

A simplified RLC model is proposed for the analysis of the ground bounce effect. A closed-form solution is presented that can be used to determine the amplitude and position of the maximum and minimum values of a chip´s generated ground bounce waveforms. The equations have a simple form and typically only the phase angle is required to evaluate the solution. The analysis was compared with the measurements of a 0.5¿m CMOS test chip demonstrating close agreement. The sheet resistance of the on-chip power supply bus plays a major role in reducing the magnitude of the ground bounce.