A Punctured Viterbi Decoder Compatible with DVB Standards

This paper presents an example of a Viterbi decoder compatible with DVB standards. The chosen architecture implements the Register Exchange Algorithm (REA). The REA has often been considered to be a more complex architectural solution than its competitor the Trace Back Algorithm (TBA). This paper aims at demonstrating that VLSI implementations of the Viterbi Algorithm are feasible using REA without great an increase in complexity compared to TBA. The chip designed in a 0.5 ¿m CMOS technology from SGS-Thomson, has been entirely synthesized from generic VHDL models. The area is almost 10 mm² for the core and 20 mm² for the chip with pads. The maximum throughput is about 70 Mbits/s.