Dual Clock Scheme for over 200MHz Synchronous DRAM System

Dual clock scheme, where master clock (CLKM) and output clock (CLKO) are applied to a SDRAM with different phase, is proposed to achieve very fast access time without area / power penalty. A circuit technique to adjust the different phase between dual clocks is described. This scheme in conjunction with 2-bit prefetch architecture enhances operating clock frequency over 200MHz without PLL/DLL on chip. An experimental dual clock 16Mbit SDRAM demonstrates the clock access time of 2.5ns.