DocumentCode
516807
Title
A fully Synchronous Circuit design for embedded DRAM
Author
Yamazaki, A. ; Okumura, N. ; Dosaka, K. ; Kumanoya, M.
Author_Institution
ULSI Lab., Mitsubishi Electric Corp., 4-1, Mizuhara, Itami, Hyogo 664, Japan
fYear
1996
fDate
17-19 Sept. 1996
Firstpage
380
Lastpage
383
Abstract
A fully synchronous circuit for embedded DRAMs is presented. It realizes accurate DRAM timing control, and easy timing adjustment. Using the circuit, software switching of the control timing is realized without difficulty. Providing handshake signals to on-chip memory-controller simplifies the memory-controller circuit in a CPU embedded DRAM.
Keywords
Central Processing Unit; Circuit synthesis; Clocks; Counting circuits; Logic circuits; Random access memory; Signal generators; Temperature control; Timing; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1996. ESSCIRC '96. Proceedings of the 22nd European
Conference_Location
Neuchatel, Switzerland
Print_ISBN
2-86332-197-8
Type
conf
Filename
5468671
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