An experiment in low-power cmos semicustom design

For semicustom cmos circuit design the sea-of-gates structure is an important structure. For low-power design, transistor dimensions need to be small. In this contribution we propose a "spider" structure. This structure creates again enough wireability for small transistor dimensions while at the same time being very suitable for the layout of DPL cmos circuits. We report results of the design of a full-adder in terms of area, speed and power dissipation in this spider structure using the DPL circuit technique showing important improvements