• DocumentCode
    516843
  • Title

    Advanced Methods for Testing VLSI Components

  • Author

    Mucha, J.

  • Author_Institution
    Univ. of Hanover, Hanover, Germany
  • fYear
    1982
  • fDate
    22-24 Sept. 1982
  • Firstpage
    84
  • Lastpage
    89
  • Abstract
    All methods for testing VLSI components are based on design for testability. Since VLSI complexity necessitates the utilization of regular design structures the emphasis of this paper is on how to exploit regularity in order to obtain easily testable components. Besides memories which are not considered here, the most important regular structures are programmable logic arrays (PLAs). Great effort has been spent on designing testable PLAs. The tendency is now towards universal test sets and self-test. Of equal importance are bit-sliced architectures. Applying the well-founded theory of iterative logic arrays (ILAs) to bit slices has produced yery promising results. Self-test is entering this area, too. An example of a 32-bit execution unit combining bit-sliced architecture and self-test concludes this paper.
  • Keywords
    VLSI; design for testability; integrated circuit testing; iterative methods; programmable logic arrays; VLSI complexity; VLSI component testing; bit-sliced architectures; design for testability; execution unit; iterative logic arrays; programmable logic arrays; self-test; universal test sets; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design for testability; Logic circuits; Logic design; Logic testing; Programmable logic arrays; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1982. ESSCIRC '82. Eighth European
  • Conference_Location
    Brussels
  • Type

    conf

  • Filename
    5468846