DocumentCode
516854
Title
NP-CMOS: A Racefree - Dynamic CMOS Technique for Pipelined Logic Structures
Author
Goncalves, N.P. ; De Man, H.
Author_Institution
ESAT, Katholieke Univ. Leuven, Leuven, Belgium
fYear
1982
fDate
22-24 Sept. 1982
Firstpage
141
Lastpage
144
Abstract
A new dynamic CMOS circuit technique uses n and p logic trees. An n input gate uses only n+2 transistors. It operates racefree from two clocks Φ and Φ̅ regardless of their overlap time. In contrast to the Domino technique, logic inversion is provided. It can be pipelined with the above (Φ, Φ̅) n-MOS clocks for much and less has the power same functional density as clocked n-MOS for much less power.
Keywords
CMOS logic circuits; Domino technique; clocked n-MOS; functional density; n logic tree; p logic tree; pipelined logic structures; racefree dynamic NP-CMOS technique; transistors; CMOS logic circuits; CMOS technology; Clocks; Delay; MOS devices; Pipeline processing; Pulse inverters; Sampling methods; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1982. ESSCIRC '82. Eighth European
Conference_Location
Brussels
Type
conf
Filename
5468857
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