Title :
A 3 μM-NMOS High-Performance LPC Speech Synthesizer Chip
Author :
Rahier, M.C. ; Defraeye, P. ; Patovan, R. ; Grassot, F. ; Obermeier, C.
Author_Institution :
Bell Telephone Manuf. Co., Antwerp, Belgium
Abstract :
A high-performance speech synthesizer chip (SPIC) based on linear predictive coding techniques is presented. The SPIC will normally be used in a 3-chip system configuration including a micro-computer and an external ROM. The speech quality can be tailored to user´s requirements. Among the specific features of the SPIC are pitch synchronous synthesis, speech parameters interpolation capability, silence and powerdown mode. Moreover the digital filter output is interpolated at a high sampling rate (32 kHz) to avoid the necessity for off-chip filtering. An 8-bit PCM output (A-law) and a 16-bit linear-coded output are provided. The SPIC can be provided in 2 different bonding configurations : for small system applications (3-chip system) or for larger system configuration.
Keywords :
MOS integrated circuits; interpolation; linear predictive coding; microcomputers; read-only storage; speech synthesis; NMOS high-performance LPC speech synthesizer chip; SPIC; digital filter output; external ROM; frequency 32 kHz; high sampling rate; linear predictive coding techniques; microcomputer; off-chip filtering; pitch synchronous synthesis; size 3 mum; speech parameter interpolation capability; word length 16 bit; word length 8 bit; Digital filters; Filtering; Interpolation; Linear predictive coding; Microcomputers; Read only memory; Sampling methods; Speech coding; Speech synthesis; Synthesizers;
Conference_Titel :
Solid-State Circuits Conference, 1982. ESSCIRC '82. Eighth European
Conference_Location :
Brussels
