DocumentCode
516868
Title
Designfeatures of a 5V Only 64K-Dynamic MOS RAM
Author
Weidlich, R.
Author_Institution
Component Div, Siemens AG, Munich, Germany
fYear
1982
fDate
22-24 Sept. 1982
Firstpage
200
Lastpage
202
Abstract
A single supply, 5 Volt 64k-bit dynamic MOS random access memory chip using some new design features such as boostet wordlines, quiet wordline flip-flops, active restore circuits, substrat bias equalization circuit etc. will be presented.
Keywords
MOS memory circuits; logic design; random-access storage; MOS RAM; active restore circuits; boostet wordlines; dynamic MOS random access memory chip; quiet wordline flip-flops; storage capacity 64 Kbit; substrat bias equalization circuit; voltage 5 V; Aluminum; Ceramics; Chip scale packaging; Circuits; Plastic packaging; Power amplifiers; Random access memory; Read-write memory; Variable structure systems; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1982. ESSCIRC '82. Eighth European
Conference_Location
Brussels
Type
conf
Filename
5468871
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