DocumentCode
516899
Title
Higher Sampling Rates in SC Circuits by On-Chip Clock-Voltage Multiplication
Author
Krummenacher, F. ; Pinier, H. ; Guillaume, A.
Author_Institution
Laboratoire d´´Ã©lectronique générale, EPFL, Lausanne, Switzerland
fYear
1983
fDate
21-23 Sept. 1983
Firstpage
123
Lastpage
126
Abstract
MOS analog switch resistance of devices with low supply voltage is drastically reduced by synchronous voltage multiplication of the clock signals. Application to a SC bandpassfilter makes a higher sampling rate (260 kHz) feasable with low supply voltage (± 1.5 V) and low power consumption (240 ¿W).
Keywords
CMOS technology; Clocks; Diodes; Inverters; Low voltage; MOS capacitors; Sampling methods; Switched capacitor circuits; Switches; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1983. ESSCIRC '83. Ninth European
Conference_Location
Lausanne, Switzerland
Print_ISBN
2-88074-021-5
Type
conf
Filename
5468907
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