Title :
A 1.5 nsec 1K Bit Bipolar RAM
Author :
Yamamoto, Yousuke ; Miyanaga, Hiroshi ; Sakai, Tetsushi
Author_Institution :
Atsugi Electrical Communication Laboratory, NTT., 1839 Ono, Atsugi-shi, Kanagawa, 243-01 JAPAN
Abstract :
A 1K bit bipolar static RAM with 1.5 nsec access time has been realized using novel circuits and super self aligned technonogy of the high performance bipolar process. These novel circuits, consisting of a fast decoder buffer, a cell circuit and a sense amplifier, lead to two times faster access time than that of conventional RAMs.
Keywords :
Capacitance; Circuit synthesis; Decoding; Gallium arsenide; Laboratories; Operational amplifiers; Random access memory; Read-write memory; Silicon; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1983. ESSCIRC '83. Ninth European
Conference_Location :
Lausanne, Switzerland
Print_ISBN :
2-88074-021-5
