A 500-Picosecond System Design Capability

A family of ultra-high speed devices has been designed to maximise the performance of digital systems. The family is based on MSI parts developed on the high performance Plessey Process III(V); these circuits offer local gate delays of 500 picoseconds and flip-flop clock rates of over 500 MHz, and enable overall `system´ gate delays of less than one nanosecond to be achieved. The performance of a scaled version of one of these circuits has improved these gate delays by a further 150 picoseconds; this improvement has been achieved by the reduction of minimum geometries to three microns. By the introduction of fundamental improvements to the basic transistor structure, and by optimisation of geometries, it will be possible to reduce the local gate delay to 200 picoseconds and the system gate delay to 500 picoseconds.