High-Speed Low-Power MOS-Comparator for 20 MHz LSI Parallel A/D Converters

A monolithic integrated comparator is presented for strobed interrogation of a difference voltage. The comparator has a dc-offset of 5 mV and provides a logic level output representing the interrogated input within 40 ns of the strobe input. Fast recovery permits operation up to 20 MHz repetition rate with a sensitivity of 20 mV. The circuit incorporates a differential amplifier stage for high common mode rejection. It uses the regenerative gain of a flip-flop to achieve rapid amplification of the input signal to a logic level. A self-adjusting bias network yields high insensivity to process parameters. Distribution of test data for delay and offset indicates the design is within the objectives for application in a fast A/D converter system.