Improvement of the Testability of LSI Circuits

The results presented in this paper form the first part of a R&D program devoted to out-line and in-line testing of LSI integrated circuits. This paper is mainly concerned with the testability of single channel MOS IC. The first part is devoted to the definition of basic assumptions related to the physical origin of failures ; these assumptions have been made taking into account 1) a theoretical evaluation of the quality of the technological process and 2) a direct inspection of a set of failed circuits chosen for their representativeness of the state of the art. The second part presents some design rules enabling the improvement of IC testability ; these rules, which are applicable during the IC implementation, tend to diminish the number of possible failures and also to facilitate the test sequence generation for the remaining failures.