Title :
Vertical Yield: An Aid in Characterising the Process Yield of Integrated Circuits
Author :
Lagerberg, J.P.L.
Author_Institution :
Philips Res. Labs., Eindhoven, Netherlands
Abstract :
In this paper the vertical yield will be introduced as a mathematical method to separate statistical and systematic faults in I.C. processes in order to characterise the process yield. A statistical process yield can be derived which offers a better indication of the improvements or the state of the art of a process than the normally used yield figure does.
Keywords :
fault diagnosis; integrated circuit yield; IC process; integrated circuit; mathematical method; statistical fault; statistical process yield; systematic fault; Circuit faults; Degradation; Fabrication; Histograms; Integrated circuit yield; Manufacturing processes; Predictive models; Q factor; Semiconductor device modeling;
Conference_Titel :
Solid State Circuits Conference - Digest of Technical Papers, 1978. ESSCIRC 78. 4th European
Conference_Location :
Amsterdam
