I2L Associative Memory Building Blocks

SFL (Substrate Fed Logic-" ), an optimised form of I2L, offers an attractive alternative to dynamic MOS and high speed bipolar technologies for the production of cost-effective associative memory building blocks. The data supporting this conclu sion are derived from an investigation of the feasibility of SFL for the fabrication of chips MB, MW and MBW, being carried out at Brunei University and funded by ACTP (Advanced Computer Techniques Project, Department of Industry) and British Aero space. Logic and layout designs for 16-word ver sions of these chips have been prepared for wafer processing at Plessey (Caswell). The awaited chips will be used for SFL chip evaluation studies and the construction of prototype associative memories at Brunei University and British Aerospace.