Memories with Josephson Junctions

Summary form only given. The talk is based on an overview which was published recently (1). For this reason, only an abstract is given here, which includes later results not contained in the aforementioned overview. The presently-known Josephson memory cells store information as persistent currents in superconducting loops, or what is equivalent as a magnetic flux in the area of the ring. This method of storage is nonvolatile and has no power consumption in the storing state. In a superconducting ring system, the magnetic flux is quantized, and cells have been built which operate either with only one flux quantum, or with many of them. For the latter cells with many flux quanta (ring cells), quite a number of designs exist. They have one or two Josephson junctions in the ring, which allow writing. An external junction which is controlled by the ring current serves for non-destructive reading of the information. The smallest cell realized had an area of 900 μm² with a 2 μm minimum line width. Switching speed was ≲ 80 ps. Cells which store information as a single-flux quantum (single flux-quantum cells = SFQ cells) in the ring, usually contain two Josephson junctions used for reading and writing. Read-out in most of these cells is destructive, but methods of reading non-destructively have also been proposed. The smallest device made had an area of ≈ 150 μm² with a minimum line width of 2 μm. The read signal had a rise time ≲ 100 ps. Recently, experimental memory models have been published with both types of cells. In these models, the drive and decode circuits use current steering in superconducting loops, with Josephson junctions as switches. The experimental model (2) with ring-type cells contains an 8 × 8 array and is fully decoded. Worst-case access time is about 4 nsec. The largest model (3) made so far was built with an array of 2000 single flux-quantum cells and part of the re- - quired drivers and decoders. It was realized to test the electrical feasibility of a 16 kBit memory chip. The results obtained indicate that such a chip is electrically feasible and would have an access time of ≈ nsec and a power consumption ≲ 40 μW. In summary, work on Josephson memory devices shows that not only cells, but, also full memory chips with drivers and decoders are feasible. These memories combine high speed with very low power-consumption.