DocumentCode
517114
Title
Design of a Very Large Reconfigurable Memory
Author
Jean-Michel, Ayache
Author_Institution
ENSIMAG, Univ. de Grenoble, Grenoble, France
fYear
1976
fDate
21-24 Sept. 1976
Firstpage
34
Lastpage
35
Abstract
We discuss in this paper, the design of a very large scale integrated memory. This memory is composed of partly faulty LSI chips and reconfiguration circuitry masking the faulty bits. Different reconfiguration policies are given leading to memory structures. Practical solutions for MK × 9 bits and 16 K × 1 bit memories are given.
Keywords
VLSI; integrated circuit design; integrated memory circuits; reconfigurable architectures; faulty bits; memory structure; partly faulty LSI chip; reconfiguration circuitry; very large reconfigurable memory design; very large scale integrated memory design; Assembly; Circuit faults; Impedance; Large scale integration; Manufacturing; Production; Programmable logic arrays; Testing; Transcoding; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Circuits Conference, 1976. ESSCIRC 76. 2nd European
Conference_Location
Toulouse
Type
conf
Filename
5469236
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