DCFL- and DPTL-Based Approaches to Self-Timed GaAs Circuits

This paper presents two GaAs MESFET-based methodologies to design self-timed circuits. The first approach uses direct-coupled FET logic (DCFL) to implement Boolean equations in sum-of-sums form, resulting in a simple and fast way to design hazard-free functional blocks in asynchronous systems. The second approach deals with an adaptation of the ratioless differential passtransistor logic (DPTL) technique to construct such functional blocks. This approach has demonstrated to be very effective in minimizing area overhead and power consumption. The methodologies are described and validated through a radix-2 redundant divider implementation.