DocumentCode
517164
Title
2.5V Novel CMOS Circuit Techniques for a 150MHz Superscalar RISC Processor
Author
Murabayashi, F. ; Yamada, H. ; Yamauchi, T. ; Ido, T. ; Nishiyama, T. ; Shimamura, K. ; Tanaka, S. ; Hotta, T. ; Shimizu, T. ; Sawamoto, H.
Author_Institution
General Purpose Computer Division, Hitachi Ltd, 1 Horiyamashita Kanagawa, 259-13 Japan
fYear
1995
fDate
19-21 Sept. 1995
Firstpage
178
Lastpage
181
Abstract
2.5V, novel CMOS circuit techniques including a noise tolerant precharge (NTP) circuit and a leakless buffer circuit are applied to a floating point macrocell for a 150MHz superscalar RISC processor. The processor makes use of a 0.3¿m CMOS technology with a 2.5V power supply and 4 metal layers. The floating point macrocell has 380k transistors and dissipates 350mW at 150MHz. The peak performance of the floating point macrocell is 300MFLOPS.
Keywords
CMOS logic circuits; CMOS process; CMOS technology; Circuit noise; Delay effects; MOS devices; MOSFETs; Macrocell networks; Reduced instruction set computing; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1995. ESSCIRC '95. Twenty-first European
Conference_Location
Lille, France
Print_ISBN
2-86332-180-3
Type
conf
Filename
5469299
Link To Document