• DocumentCode
    517186
  • Title

    A Low-Power High-Speed Self-Calibrated Differential Comparator

  • Author

    Silva, José ; Rodrigo, Paulo ; Leme, C.Azeredo ; Franca, J.E.

  • Author_Institution
    Instituto Superior Técnico, IST Centre for Microsystems, Integrated Circuits and Systems Group, Av. Rovisco Pais, 1096 Lisboa Codex, PORTUGAL. Phone: +351-1-8417674, Fax: +351-1-8417675
  • fYear
    1995
  • fDate
    19-21 Sept. 1995
  • Firstpage
    90
  • Lastpage
    93
  • Abstract
    A self-calibrated differential voltage comparator with a high speed/power ratio is presented. The comparator employs a triple differential input transconductance stage followed by a regenerative flip-flop and an output latch, and achieves a resolution of 1 mV at 40 MHz with less than 300 ¿W of total power dissipation. Fabricated in 1.2 ¿m CMOS technology, the circuit occupies 200 × 100 ¿m2 of silicon area.
  • Keywords
    CMOS technology; Calibration; Circuits; Clocks; Latches; Logic arrays; Power dissipation; Registers; Transconductance; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1995. ESSCIRC '95. Twenty-first European
  • Conference_Location
    Lille, France
  • Print_ISBN
    2-86332-180-3
  • Type

    conf

  • Filename
    5469321
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=517186