A 10 ps Resolution 1.6 ns Tuning Range CMOS Delay Line for Clock Deskewing in Data Recovery Systems

This paper describes the realization of a high resolution CMOS delay line topology. Using on-chip microstrip lines, it is possible to realize a resolution of 10 ps. Cascading 3 different delay lines gives a tuning range of more than 1.6 ns. The delay elements are digital code controlled which makes integration with the DSP in a CMOS process possible. The realized IC is designed for use in the deskewing management for a 622 Mb/s communication protocol (B-ISDN).