DocumentCode
517214
Title
Microcell - A Design Technique for Random Logic
Author
Sumerling, G.W. ; Prior, B.J. ; Hollock, S.
Author_Institution
Plessey Research (Caswell) Limited, Allen Clark Research Centre, Caswell, Towcester, Northamptonshire NN12 8EQ, U.K.
fYear
1979
fDate
18-21 Sept. 1979
Firstpage
61
Lastpage
63
Keywords
Costs; Integrated circuit interconnections; Integrated circuit technology; Integrated circuit yield; Large scale integration; Logic design; Logic gates; Microcell networks; Routing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Circuits Conference - ESSCIRC 79, Fifth European
Conference_Location
Southampton, UK
Print_ISBN
0-85296-208-8
Type
conf
Filename
5469349
Link To Document