DocumentCode
517243
Title
A Novel Bit-Level Systolic Array Median Filter
Author
Roncella, R. ; Saletti, R. ; Terreni, P.
Author_Institution
Dipartimento di Ingegneria delllnformazione: Elettronica, Informatica, Telecomunicazioni, Universit? di Pisa, Via Diotisalvi 2, 56126 Pisa, Italy. tel. + 39-50-550100, fax +39-50-555057, telex 500104 FINGPII
Volume
1
fYear
1991
fDate
11-13 Sept. 1991
Firstpage
97
Lastpage
100
Abstract
This work describes a single-chip VLSI median filter in which a new algorithm of complexity linearly dependent on the filter window length is implemented as a bit-level systolic array. The filter has a window of 25 samples and has been tested at a clock frequency over 70 MHz.
Keywords
Circuit testing; Clocks; Digital filters; Digital signal processing; Frequency; Hardware; Signal processing; Signal processing algorithms; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1991. ESSCIRC '91. Proceedings - Seventeenth European
Conference_Location
Milan, Italy
Type
conf
Filename
5469379
Link To Document