Title :
The design of LDPC decoder based on FPGA Programming in C
Author :
Zhang, Pei ; Tao, Zhi-Fu ; Liu, Tao ; Wang, Yi-Ming
Author_Institution :
Suzhou Vocational Univ., Suzhou, China
Abstract :
A new design approach of the LDPC decoder based on FPGA Impulse C Programming is proposed. The latest technique of Impulse C programming is used to implement hardware circuit, which is more efficient than the traditional HDL method. The decoder for a family of (3,6) LDPC Codes with 0.5 code rate and the block size of 2500 bits is implemented on Xilinx Virtex2 XC2V2000. When the maximum iteration time is 10 and the frequency is clocked at 50MHz, the throughput is 10 Mbps.
Keywords :
C language; field programmable gate arrays; hardware description languages; parity check codes; FPGA impulse C programming; FPGA programming; HDL method; LDPC decoder; Xilinx Virtex2 XC2V2000; hardware circuit; Algorithm design and analysis; Application software; Circuits; Embedded system; Field programmable gate arrays; Hardware; Iterative decoding; Parallel processing; Parallel programming; Parity check codes; Field Programmable Gate Array; Impulse C programming; Low-Density Parity-Check Codes; decoder;
Conference_Titel :
Networking and Digital Society (ICNDS), 2010 2nd International Conference on
Conference_Location :
Wenzhou
Print_ISBN :
978-1-4244-5162-3
DOI :
10.1109/ICNDS.2010.5479239
