Title :
MALsim: A functional-level parallel simulation platform for CMPs
Author :
Sui, Xiufeng ; Wu, Junmin ; Yin, Wei ; Zhou, Dapeng ; Gong, Zhe
Author_Institution :
Sch. of Comput. Sci. & Technol., Univ. of Sci. & Technol. of China, Hefei, China
Abstract :
Computer system simulation, including both functional level and cycle accurate level, is a crucial method for computer architecture design. And functional simulation is also called simulator kernel. It is built as an autonomous library and provides an interface to the rest of the simulator. And it´s really important for system verification and system software development. However, as the approaching of the multicore era, the fast simulation of chip multiprocessors (CMPs) is becoming a critical challenge to the architecture research community, since the speed of functional simulator suffers from superlinear slowdown as the number of cores increases. Parallel simulation is an efficient way to accelerate architecture simulation of CMPs. In this paper, we implement a parallel functional simulator called MALsim. Our work can be divided into two parts: 1) the parallelization based on multiprogrammed workloads, and 2) the parallelization based on multithreaded workloads. We implement the parallel functional simulator using POSIX threads on a multi-core host system. The evaluations show that our MALsim kernel can reach the average speedup of 1.748, 3.644, 7.372, 15.628 with 2, 4, 8, 16 threads respectively when running multiprogrammed workloads, and it will achieve the average speedup of 1.692, 2.76, 3.833, 5.292 with 2, 4, 8, 16 threads respectively when running multithreaded workloads.
Keywords :
microprocessor chips; multiprocessing systems; parallel architectures; CMP; MALsim kernel; POSIX threads; autonomous library; chip multiprocessor simulation; computer architecture design; computer system simulation; cycle accurate level; functional level; functional-level parallel simulation platform; multicore host system; simulator kernel; system software development; system verification; Computational modeling; Computer architecture; Computer simulation; Hardware; Kernel; Multicore processing; Protection; Software libraries; Software performance; Yarn;
Conference_Titel :
Computer Engineering and Technology (ICCET), 2010 2nd International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4244-6347-3
DOI :
10.1109/ICCET.2010.5485532