Power optimization in 70nm technology

Author

Jalali, Mohammad Jafar Pour ; Rezaee, Alireza

Author_Institution

Buinzahra Branch, Islamic Azad Univ., Buinzahra, Iran

Volume

3

fYear

2010

fDate

16-18 April 2010

Abstract

In this article, the speed and power dissipation of a 16-bit carry skip adder will be optimized using different optimization methods. This adder is implemented in 70 nm technology. First the worst carry propagation time will be reduced by changing logic style and using Genetic Algorithm to optimize the skip network of the circuit. And then the power dissipation of the circuit will be optimized by applying MTCMOS technology and Genetic Algorithm optimization on feature size of the transistors. With these methods we reached 7% improvement in circuit performance and 44% reduction in power consumption of the circuit.

Keywords

CMOS logic circuits; adders; carry logic; circuit optimisation; genetic algorithms; nanoelectronics; 16-bit carry skip adder; MTCMOS technology; carry propagation time; circuit performance; genetic algorithm; logic style; power dissipation; power optimization; size 70 nm; skip network; transistor feature size; word length 16 bit; Adders; CMOS technology; Circuit optimization; Energy consumption; Genetic algorithms; Logic; Low voltage; Optimization methods; Power dissipation; Signal generators; 70nm technology; MTCMOS; carry; improvement; power;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Engineering and Technology (ICCET), 2010 2nd International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-6347-3

Type

conf

DOI

10.1109/ICCET.2010.5485803

Filename

5485803