Feasibility study of a CMOS-compatible integrated solar photovoltaic cell array

Due to the low power consumption of sensors resulted by recent developments solar energy seems to be an attractive power source for self-powered devices. A proposal of a chip-scale solar module was given by Perlaky et al, containing a possible structure and a model for the proposed structure. This paper gives a more sophisticated model of the structure proposed in by taking into account the parasitic transistor present in the structure. Based on this model simulations are performed and some crucial issues of the structure are detected. Finally a modified structure of a chip-scale solar module is presented, that incorporates solutions for the issues found during simulations.