FPGA-based optimized architecture for face recognition using fixed point Householder algorithm

Eigen values evaluation is the fundamental part usually for real-time pattern recognition applications but computational intensive. Numerically calculated Eigen values based on floating point operations induce errors due to rounding and truncation effects, and the error increases further when fixed point operations are involved. On the other hand, fixed point operations are time efficient for hardware implementation. A technique has been devised to implement fixed point Householder (HH) on FPGA by developing a co-design architecture which allows efficient evaluation of Eigen values within acceptable error limits by adjusting binary bit position in fixed point operations. A relationship has been developed to define error bounds for HH on FPGA. The validity of the proposed system is demonstrated by comparing the fixed and floating point data using six different image resolutions. It is shown that the proposed architecture is 30% time efficient compared to a floating point system and .01% less error than floating point.