DocumentCode :
519117
Title :
Worst-case timing analysis in UDSM era
Author :
An, Ji Yeon ; Kim, Taehoon ; Yang, Hyung Gyun ; Kim, Young Hwan
Author_Institution :
Div. of Electr. & Comput. Eng., Pohang Univ. of Sci. & Technol., Pohang, South Korea
fYear :
2010
fDate :
19-21 May 2010
Firstpage :
376
Lastpage :
379
Abstract :
Moving to deeper in the ultra-deep sub-micron (UDSM) era continuously increases process variation. Although reliable timing analysis is necessary to ensure quality design, the increase of process variation tends to degrade the validity of the worst-case corner (WC) timing analysis. In this paper, we investigate the validity of WC timing analysis, as compared to statistical static timing analysis, under the UDSM design environment. Experimental results indicated that even the 3σ values of 10% in die-to-die (D2D) and within-die (WID) variations induced the WC timing analysis to make acceptably large overestimation, degrading its validity seriously. In addition, we found that the WID variation is more important than the D2D variation in maintaining the validity of WC timing analysis.
Keywords :
statistical analysis; timing circuits; UDSM design; die-to-die variation; statistical static timing analysis; ultra-deep submicron era; within-die variation; worst-case timing analysis; Circuit analysis; Circuit analysis computing; Computational complexity; Degradation; Delay; Design engineering; Information analysis; Optical wavelength conversion; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Engineering/Electronics Computer Telecommunications and Information Technology (ECTI-CON), 2010 International Conference on
Conference_Location :
Chaing Mai
Print_ISBN :
978-1-4244-5606-2
Electronic_ISBN :
978-1-4244-5607-9
Type :
conf
Filename :
5491465
Link To Document :
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